The reason is that the sign bit is treated in the same way as the other bits although the symbol “1” at the sign bit represents a value − 1 while the symbol “1” at other locations represents a value 1. However, this scheme seems to give a wrong answer for the case in Example 1. Application of this scheme to Example 2 provides the correct result. Scaling the output by a factor of 0.5 generates 0.001, which is a better result. In the previous example, a + b without input scaling should be 00.010. A non-zero result would become a zero.Ī better way to handle the overflow problem is to use output scaling. If the input scaling scheme were used in this addition, 0.000 and 0.000 would be the inputs to the 4-bit adder and the result would be 0.000. The following example shows an extreme case. If several additions are performed in a row, the final result may suffer from underflow. A problem associated with such an input scaling scheme is the lose of precision. This can be called input-scaling because the inputs to the binary adder are scaled. A conventional way to avoid this problem is to scale the inputs to the binary adder by a factor of 0.5 so that the result is guaranteed to be in the number system. This is called an overflow problem in binary addition because the answer of a + b is larger than 1 which cannot be represented in the number system although both a and b are in the number system. If we discard the highest bit again, we have 1.010 = -0.75, which is obviously a wrong answer. If we discard the highest bit (1 in this case), we obtain 0.010 = 0.25, which is the correct answer. In an adder design, overflow is the first problem we have to consider. For example, replacing “A * 9” with “(A SHL 3) + A” results in at least a 40-percent reduction in area. In fact, a little algebra also goes a long way in FPGAs. Similarly, when using multipliers, “A * 2” can be implemented much more efficiently as “A SHL 1” (which translates to “A shifted left by one bit”), while “A * 3” would be better implemented as “(A SHL 1) + A.” For example, “A + 2” can be implemented more efficiently as “A + 1 with carry-in,” while “A – 2” would be better implemented as “A – 1 with carry-in.” When using an adder with constants, a little thought goes a long way. This may work very efficiently in the case of a gate array device, for example, but it will typically result in a very bad FPGA implementation. In certain cases, ASIC designers sometimes employ special versions using combinations of half-adders and full-adders. Clive Max Maxfield, in FPGAs: Instant Access, 2008 Use Constants WiselyĪdders are the most used of the more complex operators in a typical design.
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